FIG. 1 illustrates the structure of a MOSFET manufactured by a conventional method. This MOSFET is manufactured in the manner described below.
That is, gate oxide film 85 is formed on silicon substrate 1, a polysilicon film is deposited thereupon, and poly gate 95 is patterned by etching the polysilicon film. An ion implantation process is carried out to form source/drain regions 22. Thereafter, oxide side wall 75 beside poly gate 95 is formed, and then insulating layer 77 (an oxide film) is deposited thereon. Finally, a contact hole is opened, and metallic contacts 79 are formed for making contact with the source/drain regions.
With such a conventional manufacturing process, there are various disadvantages as described below.
First, if a conventional photolithographic process is used and the pattern size is reduced to a very fine scale, optical interference and diffraction effects are increased. Consequently, the resolution is not enough to perform a process for elements of 0.5 .mu.m scale or below.
Second, even if a phase shifting photolithographic technique is used, a self aligned gate formation process is not utilized, and the characteristics of the MOSFET can become unstable.
Third, even though a 0.2 .mu.m scale device may be formed, the area of the source/drain regions has to be sufficiently large in order to form the source/drain contacts.